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TRF7970A
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
The transmit system in passive target mode differs from active target and operates similar to the standard
tag. There is no automatic RF collision avoidance sequence, and encoders are used to code the data for
ISO14443A\B tag (at 106 kbps, to start) or FeliCa (at 212 kbps, to start) format. The collision avoidance
must be handled by the firmware on the connected MCU. The coding system adds all of the SOF, EOF,
CRC, parity bits, and synchronization bytes that are required by protocol. On the physical level, the
modulation of the initiator's RF field is done by changing the termination impedance of the antenna
between 4 Ω and open.
6.1.3.3
Card Emulation
The chip can enter this mode by setting appropriate option bits. There are two options to emulate a card.
For ISO14443A\B, the emulation supports 106-kbps data rate to start. For ISO14443A, the anticollision
algorithm can be performed using an internal state machine, which relieves the MCU of any real-time
tasks. The unique ID required for anticollision is provided by the MCU after wake-up of the system.
6.2
System Block Diagram
Figure 6-2 shows a block diagram of the TRF7970A.
VDD_I/O
RX_IN1
MUX
PHASE &
AMPLITUDE
DETECTOR
GAIN
RSSI
(AUX)
LOGIC
STATE
I/O_0
I/O_1
RF LEVEL
DETECTOR
CONTROL
LOGIC
I/O_2
RX_IN2
RSSI
(EXTERNAL)
[CONTROL
I/O_3
PHASE &
AMPLITUDE
GAIN
RSSI
(MAIN)
REGISTERS &
COMMAND
LOGIC]
I/O_4
I/O_5
VDD_PA
DETECTOR
FILTER
& AGC
DIGITIZER
MCU
INTERFACE
I/O_6
I/O_7
ISO
PROTOCOL
HANDLING
DECODER
IRQ
TX_OUT
TRANSMITTER ANALOG
FRONT END
FRAMING
BIT
FRAMING
127-BYTE
FIFO
SYS_CLK
DATA _CLK
SERIAL
VIN
VSS_PA
EN
EN2
ASK/OOK
MOD
OSC_IN
OSC_OUT
CONVERSION
CRC & PARITY
DIGITAL CONTROL
STATE MACHINE
VOLTAGE SUPPLY REGULATOR SYSTEMS
(SUPPLY REGULATORS AND REFERENCE VOLTAGES)
CRYSTAL OR OSCILLATOR
TIMING SYSTEM
Figure 6-2. System Block Diagram
VDD_A
BAND_GAP
VSS_A
VDD_RF
VSS_RF
VDD_X
VSS
VSS_D
6.3
Power Supplies
The TRF7970A positive supply input V IN (pin 2) sources three internal regulators with output voltages
V DD_RF , V DD_A and V DD_X . All regulators use external bypass capacitors for supply noise filtering and must
be connected as indicated in reference schematics. These regulators provide a high power supply reject
ratio (PSRR) as required for RFID reader systems. All regulators are supplied by V IN (pin 2).
The regulators are not independent and have common control bits in register 0x0B for output voltage
setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B,
bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the
highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode
allows the user to manually configure the regulator settings.
14
Detailed Description
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